In modern semiconductor technology, great amounts of functionality are provided within a single chip, which is often implemented on a single semiconductor die. For example, multi-core processors have been developed that include multiple processing cores formed on a single semiconductor die. It is further anticipated that greater amounts of functionality in the form of disparate intellectual property (IP) logic blocks will continue to be integrated on a single semiconductor die.
One complexity that exists with regard to incorporating different functional logic blocks is that these different logic blocks can operate in different voltage and frequency domains. As such, communication between these logic blocks becomes complex and can require significant clock skew and voltage domain crossing logic, which can consume excessive latency, die size and power.